VHDL-Based Implementation of Chrome Dino Game

GitHub Repo View the code on GitHub


Welcome to the Chrome Dino Game repository! This repo contains a complete reconstruction of the famous “Chrome Dino” game, designed to run on the Cyclone V GX FPGA using pure VHDL. Let’s have a quick Demo of the Game in video below.

Watch my video on youtube (click on the picture below):

Watch the video

Why do I Build games?
In the spring of 2026, I decided that I wanted to truly master RTL design, and I asked myself: what could be more joyful than building games in hardware?=)))
That idea became the start of my FPGA game‑development adventure. The Dino Game was my third serious milestone (and honestly, my favorite one), and through it I practiced real RTL design, timing, video output, and hardware‑driven game logic.


Project Overview

The goal of this project is to implement the Chrome Dino game On FPGA. The game allows a player to control a dinosaur, jumping or crawling to avoid obstacles like cactuses and bats. As the game progresses, the player’s score is displayed on the board’s seven-segment displays.


System Architecture

The architecture is modular. At the center is the Top-Level Module (top/dino_top), which connects the inputs (buttons) to the logic and outputs (HDMI and Audio).

The Dino Game’s Block Diagram:

The Dino Game's Diagram

State Machine(FSM):

The logic/dino_SM.vhd module acts as the central controller for the game, utilizing a synchronous finite state machine to manage three distinct operational states.

The Dino Game's FSM

States of the State Machine

The state machine’s main job is to coordinate the behavior of other modules by toggling specific enable signals. It outputs control signals such as o_run_en, o_jump_en, and o_crawl_en to determine which visual frame of the dinosaur should be drawn on the screen and whether obstacles should continue moving. Additionally, it manages the o_reset_game signal to clear scores and positions between game sessions.


Detailed Module Explanation

Core Game Logic

Graphics and Display

Audio System

Utilities and UI


Setup Guide

The project is tested on Altera Cyclone V GX Starter Kit.

For the Cyclone V GX FPGA Board, I have used the follwing Pinout table:
Click here to open the Pinout-Table.CSV

How to Play: